Some circuit design tools provide developers with the capability to customize generic forms of circuit designs in order to implement circuits that are suitable for each developer's particular application. The generic forms of the circuit designs are sometimes referred to as logic cores or intellectual property (IP) cores. Developers rely on logic cores to reduce development time and costs.
The parameterization available for some logic cores may result in a very large number of possible combinations of signal connections between circuit blocks of the logic core. Verifying that the signal connections are correct is imperative. However, using a functional verification approach to verify correct signal connectivity would consume a large number of simulation resources and involve significant efforts to develop suitable test benches. The number of simulation runs required to check the correct signal connections may be very large in logic cores having a large number of connections to check. For example, in gigabit transceivers that are available in devices from XILINX®, Inc., the transceiver has 52 channels, and each channel has 335 signal pins, 66 quad pins, and 30 pins for helper logic blocks. This results in 22,412 (52*(335+66+30)) pins with a large number of signal connections between those pins to check.